An A/D converter is a kind of interface circuit, which converts analog signals to digital signals; it has come to enjoy wide use with the spread of digital technology and microprocessor technology. In broad terms, A/D converters can be divided into 3 conversion methods: the flash (serial) type, the successive integration type, and the integrating type; however, in applications where a high conversion speed is required, the flash type is in widest use.
FIG. 22 shows a circuit configuration of a representative conventional flash A/D converter. In a flash A/D converter with a resolution of N bits, (2.sup.N -1) comparators are connected in series to the input analog signal. Therefore, for 8 bits, as shown in FIG. 22, 255 comparators CO1, CO2, . . . CO255 are provided, and one of the input terminals to each of these is the analog signal input terminal 100, connected in series (in common). To the other input terminal on these comparators CO1, CO2, CO255 is applied one of 255 comparison reference voltages V1, V2, . . . V255, which are obtained by voltage dividing a reference voltage (Vref, T -Vref, B ) corresponding to full scale, using 255 equal-value resistors r1, r2, . . . r 255.
In each comparator COi a comparison is made between the input analog signal VIN voltage level and the comparison reference voltage Vi. An H level output voltage is obtained on the noninverting output of each comparator COi when the relationship VIN&gt;Vi is established. When the relationship VIN&lt;Vi is established, an L level voltage is obtained on the noninverting output of each comparator COi. These comparators CO1, CO2, . . . CO255 are latched comparators; they hold their output voltage levels when the clock is input from clock driver 102.
An equal number (255) of AND circuits AG1, AG2, . . . AG255 is provided on the output side of these comparators CO1, CO2, . . . CO255, and the noninverting output of each comparator COi is connected to one of the input terminals of the corresponding AND gate AGi, while the inverting input terminal is connected to the other input terminal of the AND gate AGi+1 corresponding to the adjacent comparator. In this manner, an H level output voltage will be obtained only at the output of the AND circuit AGi connected to the noninverting output of the comparator COi on which an H output voltage level exists at the lowest comparison reference voltage; an L level output voltage is obtained at the output of other AND circuits. Encoder 104 converts the 255 binary logical outputs input from the outputs of AND circuits AG1, AG2, . . . AG255 to an 8-bit signal. 8-bit digital signal output from encoder 104 is temporarily stored in output buffer 106, and this is then sent out in sync with the clock.
FIG. 23 shows a circuit diagram for a 2 step flash A/D converter, well known as an improvement on the flash A/D converter. In a 2 step flash type, the A/D converter conversion operation is divided into an upper and lower step.
In FIG. 23, the analog VIN signal input to analog signal input terminal 110 is applied to one of the input terminals of differential amplifier 114 through sample-and-hold circuit 112 as well as to upper A/D converter 116. Upper A/D converter 116 A/D converts the input analog signal VIN to, for example, upper 4-bit digital data item. These upper 4-bit data items are reconverted to an analog signal by D/A converter 118, whereupon it is input to the other input terminal on differential amplifier 114. Differential amplifier 114 subtracts the upper 4-bit analog portion from input analog signal VIN and applies the difference to lower A/D converter 120. Lower A/D converter 120 does an A/D conversion of the input differential signal to, for example, a 4-bit data item. The 4-bit item data output from lower A/D converter 120 is combined as the lower 4 bits with the upper 4 bits from upper A/D converter 116. In the end an 8-bit digital signal is obtained.
With the 2 step flash type, because, as we have described, the A/D conversion operation is conducted twice (2 step operation), one for the upper and one for the lower bits, a sample-and-hold circuit 112 is provided so that the input analog signal does not change during the A/D conversion.
Problems the invention aims to solve
In the flash A/D converter representative of conventional technology described above, the comparison operation takes place in all comparators simultaneously, so a very high conversion speed can be obtained; however, the number of circuit elements expands exponentially as resolution increases, with the disadvantage of increasing the scale of the circuit. As described above, if resolution is N bits, (2.sup.N -1) comparators are required; however, that which has an even larger effect on circuit real estate is encoders. FIG. 24 shows a circuit diagram for a common encoder. This encoder circuit is used for a 4-bit flash A/D converter, so it has 15 binary logic voltage inputs Y1-Y15, and internal transistor logic circuits encode those binary logic voltages to a 4-bit (D0,D1,D2,D3) digital signal. So for a 4-bit encoder we have 15 inputs; for an 8-bit this becomes 255, and for a 10-bit it becomes 1023, with the number of elements in the internal transistor logic circuitry expanding exponentially with the increase in input terminals, and circuit area grows enormously.
On that point, the 2 step flash type makes it possible to greatly decrease the number of elements and reduce circuit area. For example, in the 2 step flash A/D converter shown in FIG. 23, the resolution of upper A/D converter 116 and lower A/D converter 120 is 4 bits in both cases, so the number of comparators required is (2.sup.4 -1)=15; even adding the two together gives only 30 comparators. This is a large reduction compared to the representative A/D converter shown in FIG. 22 (255 comparators). Also, since the number of comparators is small, a small number of encoder input terminals will also suffice. However, because 2 step flash A/D converters divide the A/D conversion operation into an upper and lower step, it is necessary to hold the input with a sample-and-hold [circuit]. There is also a basic disadvantage in the limitation of conversion speed. Furthermore, because the analog signal is roughly A/D converted by the upper A/D converter, the upper bit accuracy is low, and this error can cause large errors in the digital signal value, requiring error correction circuitry.